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MC54/74F259 8-BIT ADDRESSABLE LATCH
The MC54/74F259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. It is a multifunctional device capable of storing single line data in eight addressable latches, and also a 1-of-8 decoder and demultiplexer with active HIGH outputs. The device also incorporates an active LOW Common Clear for resetting all latches, as well as an active LOW Enable. * Serial-to-Parallel Conversion * Eight Bits of Storage with Output of Each Bit Available * Random (Addressable) Data Entry * Active High Demultiplexing or Decoding Capability * Easily Expandable * Common Clear
8-BIT ADDRESSABLE LATCH
FASTTM SCHOTTKY TTL
J SUFFIX CERAMIC CASE 620-09
16
FUNCTIONAL DESCRIPTION The MC54/74F259 has four modes of operation as shown in the Mode Select Table. In the addressable latch mode, data on the Data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states in the memory mode. All the latches remain in their previous state and are unaffected by the Data or Address inputs. In the one-of-eight decoding or demultiplexing mode, the addressed output will follow the state of the D input with all other outputs in the LOW state. In the clear mode all outputs are LOW and unaffected by the address and data inputs. When operating the MC54/74F259 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The Truth Table below summarizes the operations of the MC54/74F259.
1
16 1
N SUFFIX PLASTIC CASE 648-08
16 1
D SUFFIX SOIC CASE 751B-03
ORDERING INFORMATION CONNECTION DIAGRAM
VCC 16 MR 15 E 14 D 13 Q7 12 Q6 11 Q5 10 Q4 9 MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC
LOGIC SYMBOL
14 13 1 2 3 D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 4 5 6 7 9 10 11 12 E 15 MR
1 A0
2 A1
3 A2
4 Q0
5 Q1
6 Q2
7 Q3
8 GND
FAST AND LS TTL DATA 4-133
MC54/74F259
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range 74 Output Current -- High Output Current -- Low 54, 74 54, 74 0 25 70 -1.0 20 Parameter 54, 74 54 Min 4.5 -55 Typ 5.0 25 Max 5.5 125 Unit V C mA mA
Q7
Q6
Q5
MR Q4
A2 A1
Q3
A0
Q2
Q1 D E Q0
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
FAST AND LS TTL DATA 4-134
MC54/74F259
MODE SELECT TABLE
E L H L H MR H H L L Mode Addressable Latch Memory Active HIGH 8-Channel Demultiplexer Clear
H = HIGH Voltage Level L = LOW Voltage Level
FUNCTION TABLE
Operating Mode Master Reset Demultiplex (Active HIGH Decoder when D = H) Inputs MR L L L L * * * L H H H H * * * H E H L L L * * * L H L L L * * * L D X d d d * * * d X d d d * * * d A0 X L H L * * * H X L H L * * * H A1 X L L H * * * H X L L H * * * H A2 X L L L * * * H X L L L * * * H Q0 L Q=d L L * * * L q0 Q=d q0 q0 * * * q0 Q1 L L Q=d L * * * L q1 q1 Q=d q1 * * * q1 Q2 L L L Q=d * * * L q2 q2 q2 Q=d * * * q2 Outputs Q3 L L L L * * * L q3 q3 q3 q3 * * * q3 Q4 L L L L * * * L q4 q4 q4 q4 * * * q4 Q5 L L L L * * * L q5 q5 q5 q5 * * * q5 Q6 L L L L * * * L q6 q6 q6 q6 * * * q6 Q7 L L L L * * * Q=d q7 q7 q7 q7 * * * Q=d
Store (Do Nothing)
Addressable Latch
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial d = HIGH or LOW Data one setup time prior to the LOW-to-HIGH Enable transition. q = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared.
FAST AND LS TTL DATA 4-135
MC54/74F259
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH VOL IIH IIL IOS Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54, 74 Output HIGH Voltage 74 Output LOW Voltage Input HIGH Current 0.1 Input LOW Current Output Short Circuit Current (Note 2) Power Supply Current Total, Output HIGH Total, Output LOW - 60 - 0.6 -150 46 75 2.7 0.5 20 V V A mA mA mA mA mA 2.5 Min 2.0 0.8 -1.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN, IIN = -18 mA IOL = -1.0 mA IOL = -1.0 mA IOL = 20 mA VCC = MIN VCC = 4.75 V VCC = MIN
VCC = MAX, VIN = 2.7 V VCC = MAX,VIN = 7.0 V VCC = MAX, VIN = 0.5 V VCC = MAX, VOUT = 0 V VCC = MAX VCC = MAX
ICC
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more then one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
54/74F TA = +25C VCC = +5.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Propagation Delay E to Qn Propagation Delay Dn to Qn Propagation Delay An to Qn Propagation Delay MR to Qn Min 4.0 3.0 3.5 3.0 3.5 4.0 5.0 Max 10.5 7.0 9.0 6.5 13 9.0 9.0 54F TA = -55 to + 125C VCC = 5.0 V 10% CL = 50 pF Min 4.0 3.0 3.5 2.5 3.5 4.0 4.5 Max 13 8.5 11.5 8.5 15.5 11 11.5 74F TA = 0 to + 70C VCC = 5.0 V 10% CL = 50 pF Min 4.0 3.0 3.5 2.5 3.5 4.0 4.5 Max 12 7.0 10 7.0 14.5 9.5 10 Unit ns ns ns ns
FAST AND LS TTL DATA 4-136
MC54/74F259
AC OPERATING REQUIREMENTS
54/74F TA = +25C VCC = +5.0 V Symbol ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tW tW Parameter Setup Time, HIGH or LOW Dn to E Hold Time, HIGH or LOW Dn to E Setup Time, HIGH or LOW A to E(a) Hold Time, HIGH or LOW A to E(b) E Pulse Width Min 4.0 4.0 2.0 2.0 4.0 4.0 0 0 4.0 4.0 Max 54F TA = -55 to +125C VCC = 5.0 10% Min 5.0 5.0 2.0 2.0 4.0 4.0 0 0 4.0 4.0 Max 74F TA = 0 to +70 C VCC = 5.0 V 10% Min 4.0 4.0 2.0 2.0 4.0 4.0 0 0 4.0 4.0 Max Unit ns ns ns ns ns ns
MR Pulse Width
a. The Address to Enable setup time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected. b. The Address to Enable hold time is the time after the LOW-to-HIGH Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected.
FAST AND LS TTL DATA 4-137

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